Implementation of a simple 8-bit SUBNEG CPU. The CPU interfaces to external SRAM memory through address output latch. CPU output can be implemented using a second output latch. The program to be executed has to be written to the SRAM by external means (e.g. a microcontroller) prior to setting CPU enable pin high. 3 inputs are provided for this purpose (CPU enable, External SRAM address latch CLK, External SRAM WEn).
3.3V SRAM memory (e.g. AS6C6264). Memory address latch (e.g. 74HC574). CPU output latch (e.g. 74HC574). Device capable of displaying 8-bit output value.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | CPU enable | SRAM address latch CLK | CPU bi-directional bus |
| 1 | External SRAM address latch CLK | SRAM OEn | CPU bi-directional bus |
| 2 | External SRAM WEn | SRAM WEn | CPU bi-directional bus |
| 3 | CPU output latch CLK | CPU bi-directional bus | |
| 4 | Internal CPU state bit 0 | CPU bi-directional bus | |
| 5 | Internal CPU state bit 1 | CPU bi-directional bus | |
| 6 | Internal CPU state bit 2 | CPU bi-directional bus | |
| 7 | Internal CPU state bit 3 | CPU bi-directional bus |