This is a minimalistic coarse-grained reconfigurable array inspired by AMD AI engine architecture. The hardware design consists of
The packets loaded by interface tiles are routed through the NoC to the compute tiles. The compute tiles process the packets and send to next compute tile or interface tile. The packets are processed in a pipelined manner.
TBA
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | data_0 | out_0 | debug_out0 |
| 1 | data_1 | out_1 | debug_out1 |
| 2 | data_2 | out_2 | debug_out2 |
| 3 | data_3 | out_3 | debug_out3 |
| 4 | data_4 | out_4 | debug_out4 |
| 5 | data_5 | out_5 | debug_out5 |
| 6 | data_6 | out_6 | debug_out6 |
| 7 | data_7 | out_7 | debug_out7 |