This is a naive implementation of an "Alternating Step Generator" (ASG) to produce bit sequences with a very long period. ASGs are characterized by their easy implementability in hardware, which is why they are a nice example for the use of SpinalHDL (the provided Verilog is generated by using SpinalHDL).
An ASG consists of three different "Linear Shift Feedback Registers" (LSFR), which must be coupled appropriately. The provided configuration is expected to have a period length of 226156424186320902518104893031800133178333732395566208938371914392362024959 cycles. If the chip could be operated by 1GHz this would be reached after 3.89 10^38 years (approximately 2.78 10^28 times the age of the universe)!
The SpinalHDL based version (including more info about ASGs) can be found at https://github.com/SteffenReith/ASG
Used connection polynoms:
private val connPolyStrR1 = "x^31+x^3+1" private val connPolyStrR2 = "x^63+x+1" private val connPolyStrR3 = "x^89+x^38+1"
Simply load the registers R1 (loadit==1), R2 (loadit == 2) and R3 (loadit == 3) with non-null seed data. Set loadit to 0 and enable to 1. A new bit is generated every clock.
No external hardware is used
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | loadIt[0] | newBit | |
| 1 | loadIt[1] | ||
| 2 | enable | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |