This project is center in the implementation of Verilog code for 4 bit Wallace tree multiplier. The design uses half adder and full adder Verilog designs. These modules will be instantiated for the implementation 4 bit Wallace multiplier.
Under test file, a wallace_tb.v code is located, this code is the testbench
You do not need any special external hardware.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui[0] | uo [0] | |
| 1 | ui[1] | uo [1] | |
| 2 | ui[2] | uo [2] | |
| 3 | ui[3] | uo [3] | |
| 4 | ui[4] | uo [4] | |
| 5 | ui[5] | uo [5] | |
| 6 | ui[6] | uo [6] | |
| 7 | ui[7] | uo [7] |