Verilog model of the SN74169.
ui_in[3:0] = A[3:0] 4b parallel load
ui_in[4] = ENPB
ui_in[5] = ENTB
ui_in[6] = LOADB
ui_in[7] = UP/DOWNB
uo_out[3:0] = Q[3:0] 4b output
uo_out[4] = RCOB
uo_out[5] = !ui_in[0] - for debugging
clk = system clock
Oscilloscope to observe the outputs.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | A0 | Q0 | |
| 1 | A1 | Q1 | |
| 2 | A2 | Q2 | |
| 3 | A3 | Q3 | |
| 4 | ENPB | RCOB | |
| 5 | ENTB | ||
| 6 | LOADB | ||
| 7 | UP |