The project consist of a RISC-V VHDL Model and supports the Tiny RV1 ISA without MUL. In addition AND and XOR are supported.
To test our design you will need to use external hardware.
To use our design you will need to use the provided spi_slave_tt06_with_memory and synthesize it for an 12 MHz FPGA.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | SPI MISO | SPI MOSI | Register_1(5) |
| 1 | unused | SPI SCLK | Register_1(6) |
| 2 | unused | SPI CS | Register_1(7) |
| 3 | unused | Register_1(0) | Register_1(8) |
| 4 | unused | Register_1(1) | Register_1(9) |
| 5 | unused | Register_1(2) | Register_1(10) |
| 6 | unused | Register_1(3) | Register_1(11) |
| 7 | unused | Register_1(4) | Register_1(12) |