This project is centerd in the implementation of a verilog code for 4 bit Wallace tree multiplier. The design uses half adder and full adder Verilog designs.
On file Test, there is a testbench call wallace_tb.v Use the code to test the code.
You do not need any special external hardware
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui[0] | uo[0] | |
| 1 | ui[1] | uo[1] | |
| 2 | ui[2] | uo[2] | |
| 3 | ui[3] | uo[3] | |
| 4 | ui[4] | uo[4] | |
| 5 | ui[5] | uo[5] | |
| 6 | ui[6] | uo[6] | |
| 7 | ui[7] | uo[7] |